Processor Wafer

Description:

Yogeeswaran Ganesan’s fabricated this four inch silicon wafer for use in experiments relating to his 2011 Rice Universtiy PhD thesis on “The Mechanical Characterization of Multi Wall Carbon Nanotubes and Related Interfaces in Nanocomposites.” Standard silicon microfabrication techniques were tailored to make microdevices on the silicon wafer to meet the needs of Ganesan’s experiments. The experiment included the use of a nanoindenter to examine the characterization of nanomaterials under a scanning electron microscope, and a novel procedure to help develop a solid understanding the physical characteristics of carbon nanotubes by examining their deformation and failure under stress and strain in real time. The microdevices on the silicon wafer provided an electrostatically actuated platform for testing the properties of individual nickel nanowires as well as multiwall carbon nanotubes to provide experimental verification of theoretical predictions of nanomaterial applications.

Location: Currently not on view (plastic box)Currently not on view

See more items in: Work and Industry: Production and Manufacturing, Industry & Manufacturing, American Enterprise

Exhibition:

Exhibition Location:

Credit Line: Gift of Yogeeswaran Ganesan

Data Source: National Museum of American History

Id Number: 2014.0039.01Catalog Number: 2014.0039.01Accession Number: 2014.0039

Object Name: processor wafer

Physical Description: silicon (overall material)Measurements: wafer: 3 7/8 in; 9.8425 cmbox: 5/8 in x 4 7/16 in; 1.5875 cm x 11.27125 cm

Guid: http://n2t.net/ark:/65665/ng49ca746ae-13a6-704b-e053-15f76fa0b4fa

Record Id: nmah_1461100

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