Processor Wafer

Yogeeswaran Ganesan’s fabricated this four inch silicon wafer for use in experiments relating to his 2011 Rice Universtiy PhD thesis on “The Mechanical Characterization of Multi Wall Carbon Nanotubes and Related Interfaces in Nanocomposites.” Standard silicon microfabrication techniques were tailored to make microdevices on the silicon wafer to meet the needs of Ganesan’s experiments. The experiment included the use of a nanoindenter to examine the characterization of nanomaterials under a scanning electron microscope, and a novel procedure to help develop a solid understanding the physical characteristics of carbon nanotubes by examining their deformation and failure under stress and strain in real time. The microdevices on the silicon wafer provided an electrostatically actuated platform for testing the properties of individual nickel nanowires as well as multiwall carbon nanotubes to provide experimental verification of theoretical predictions of nanomaterial applications.
Object Name
processor wafer
Physical Description
silicon (overall material)
wafer: 3 7/8 in; 9.8425 cm
box: 5/8 in x 4 7/16 in; 1.5875 cm x 11.27125 cm
ID Number
catalog number
accession number
Industry & Manufacturing
American Enterprise
See more items in
Work and Industry: Production and Manufacturing
American Enterprise
American Enterprise
Data Source
National Museum of American History, Kenneth E. Behring Center
Credit Line
Gift of Yogeeswaran Ganesan

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