Intel Tri-Gate Test Wafer
Intel Tri-Gate Test Wafer
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- Description
- This is an uncut silicon wafer containing Intel’s tri-gate transistor technology, the 22 nanometer microprocessor architecture used in Intel’s Ivy Bridge and Haswell CPU’s. The test structures on this wafer were designed by Uday Shah and Ravi Pillarisetty and provided a proof-of-concept to Intel that 3D tri-gate transistor technology was commercially viable. While the architecture was originally announced in 2002, Intel’s Ivy Bridge CPU’s didn’t hit the market until late 2011, a testimony to the highly intricate nature of microprocessor production.
- The highly pure silicon wafer provides the substrate for transistors on the integrated circuits that make up microprocessors. The wiring circuity is imprinted on the silicon via a microscopic photolithography process. Intel’s tri-gate technology refers to the process of stacking a single logic gate on top of two vertical gates, creating conducting channels on three sides of a vertical fin structure, a three dimensional transistor that results in lower energy consumption and increased speed.
- Location
- Currently not on view (plastic case)
- Object Name
- wafer
- date made
- 2006
- maker
- Intel Corporation
- Physical Description
- plastic (case material)
- silicon (overallwafer material)
- Measurements
- case: 1 in x 14 1/4 in x 12 3/4 in; 2.54 cm x 36.195 cm x 32.385 cm
- wafer: 1/32 in x 11 3/4 in;.07938 cm x 29.845 cm
- ID Number
- 2014.0098.01
- catalog number
- 2014.0098.01
- accession number
- 2014.0098
- Credit Line
- Gift of Intel Corporation
- See more items in
- Work and Industry: Production and Manufacturing
- Industry & Manufacturing
- Computers & Business Machines
- American Enterprise
- Exhibition
- American Enterprise (wafer)
- Exhibition Location
- National Museum of American History
- Data Source
- National Museum of American History
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